| CPC H04L 45/60 (2013.01) [G06F 13/1668 (2013.01); G06F 15/163 (2013.01); G06F 15/7825 (2013.01); H04L 45/566 (2013.01)] | 23 Claims |
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1. A memory attachment and routing chip comprising:
a single die having a set of external ports, at least one memory attachment interface comprising a memory controller and configured to attach to external memory, and a fabric core in which routing logic is implemented,
wherein the routing logic is configured to (i) receive a first packet of a first type from a first port of the set of external ports, the first type being a memory access packet comprising a memory address which lies in a range of memory addresses associated with the memory attachment and routing chip, to detect the memory address and to route the first packet of the first type to the memory attachment interface, and to (ii) receive a second packet of a second type, the second type being an inter-processor packet comprising a destination identifier identifying a processing chip external to the memory attachment and routing chip and to route the second packet to a second port of the set of external ports, the second port being selected based on the destination identifier.
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18. A computer comprising:
a first memory attachment and routing chip and a second memory attachment and routing chip, each comprising:
a single die having a set of external ports,
at least one memory attachment interface comprising a memory controller and configured to attach to external memory, and
a fabric core in which routing logic is implemented,
wherein the routing logic is configured to:
(i) receive a first packet of a first type from a first port of the set of external ports, the first type being a memory access packet comprising a memory address which lies in a range of memory addresses associated with the memory attachment and routing chip, to detect the memory address and to route the first packet to the memory attachment interface, and
(ii) to receive a second packet of a second type, the second type being an inter-processor packet comprising a destination identifier identifying a processing chip external to the memory attachment and routing chip and to route the second packet to a second port of the set of external ports, the second port being selected based on the destination identifier; and
a first computer device and a second computer device, the first computer device being connected to the first ports of the first memory attachment and routing chip and of the second memory attachment and routing chip via respective first and second links, the second computer device being connected to the second ports of the first memory attachment and routing chip and to the second memory attachment and routing chip via respective third and fourth links,
the first computer device comprising first processing circuitry configured to execute one or more computer programs and being connected to the first and second links to transmit and receive messages via the first and second links.
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20. A method of routing packets in a computer system comprising a cluster of processor chips, the method comprising:
transmitting a packet from a designated external port of a first processor chip of the cluster of processor chips, the designated external port being connected to a memory attachment and routing chip of the cluster of processor chips, wherein the packet contains destination information;
at routing logic of the memory attachment and routing chip, determining from the destination information that the packet is destined for either: memory attached to the memory attachment and routing chip or a component attached to an external port of the memory attachment and routing chip; and
routing the packet according to the destination information.
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