| CPC H04L 43/12 (2013.01) [H04L 45/02 (2013.01); H04L 45/74 (2013.01)] | 20 Claims |

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9. A packet switching system comprising:
at least one processor; and
at least one memory storing instructions, which when executed by the at least one processor, causes the packet switching system to:
select a first network node to second network node pairing to perform connectivity testing;
configure egress processing towards the first network node to intercept test reply packets;
create a test request packet including at least a source address of the first network node and a destination of the second network node;
inject the test request packet into a data plane processing path, wherein the injecting occurs before ingress processing at the first network node; and
in response to intercepting the test reply packet from the injecting of the test request packet, update a node-to-node connectivity tracking table between the first network node and the second network node and remove or suspend the egress processing towards the first network node.
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