| CPC H03M 13/3738 (2013.01) [H03M 13/3715 (2013.01); G06F 11/1012 (2013.01); G06F 11/1044 (2013.01)] | 20 Claims |

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1. An error correction code (ECC) decoder comprising:
an input manager configured to sequentially receive a first read data including a plurality of data units read from a plurality of sectors in a memory cell array of a nonvolatile memory device, by unit of sector;
a pre-decoder configured to sequentially receive the first read data by unit of sector, in parallel with the input manager receiving the first read data and configured to generate a respective syndrome of each of the plurality of data units sequentially; and
a main decoder configured to sequentially perform a first ECC decoding on the first read data based on the respective syndrome, by unit of sector,
wherein, the input manager includes a defective sector buffer and is configured to:
in response to the first ECC decoding on a first data unit of the plurality of data units being failed, store the first data unit in the defective sector buffer; and
in response to the first ECC decoding on a second data unit of the plurality of data units being failed, selectively store the second data unit in the defective sector buffer based on an expected error count of each of the first data unit and the second data unit, and
wherein the main decoder is configured to perform a second ECC decoding on a defective data unit stored in the defective sector buffer and receive a second read data from a selected sector corresponding to the defective data unit, from among the plurality of sectors.
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