US 12,273,125 B2
Byte error correction
Thomas Kern, Aschheim (DE); Thomas Rabenalt, Unterhaching (DE); and Michael Goessel, Mahlow (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Sep. 14, 2022, as Appl. No. 17/944,510.
Claims priority of application No. 10 2021 123 727.0 (DE), filed on Sep. 14, 2021.
Prior Publication US 2023/0091457 A1, Mar. 23, 2023
Int. Cl. H03M 13/15 (2006.01); H03M 13/00 (2006.01)
CPC H03M 13/1575 (2013.01) [H03M 13/611 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A device comprising a memory and an error-correcting circuit arrangement, the circuit arrangement configured to:
access a code word of a Reed Solomon error-correcting code, the code word comprising a plurality of bytes having corresponding positions,
determine a first byte error position signal for a first erroneous byte of the code word,
determine a first byte error correction value for correcting the first erroneous byte identified by the first byte error position signal, the first byte error correction value determined using a first value and a second value determined for each of at least two byte positions based on a coefficient of a locator polynomial, and
correct the first erroneous byte based on the first byte error correction value.