US 12,273,117 B2
Low noise phase lock loop (PLL) circuit
Anand Kumar, Noida (IN); and Prashutosh Gupta, Ballia (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Oct. 19, 2022, as Appl. No. 17/969,251.
Claims priority of provisional application 63/281,808, filed on Nov. 22, 2021.
Prior Publication US 2023/0163769 A1, May 25, 2023
Int. Cl. H03L 7/197 (2006.01); H03L 7/089 (2006.01); H03L 7/093 (2006.01); H03L 7/099 (2006.01)
CPC H03L 7/1974 (2013.01) [H03L 7/0893 (2013.01); H03L 7/093 (2013.01); H03L 7/0995 (2013.01); H03L 2207/06 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A phase lock loop (PLL) circuit, comprising:
a phase-frequency detector (PFD) circuit configured to determine a difference between a reference clock signal and a feedback clock signal and generate up/down control signals in response to said difference;
a first charge pump operating in response to the up/down control signals to generate a first charge pump current;
a loop filter comprising a capacitor but no resistor that filters the first charge pump signal to generate a control voltage;
a second charge pump operating in response to the up/down control signals to generate a second charge pump current, wherein the second charge pump further receives the control voltage and the second charge pump current is generated dependent on both the control voltage and the up/down control signals;
a voltage controlled oscillator comprising:
a first transconductance circuit controlled by said control voltage to generate a first transconductance current;
a current summing node configured to sum the first transconductance current with the second charge pump current to generate a control current; and
a current controlled oscillator configured to generate an oscillating output signal having a frequency controlled by said control current; and
a divider circuit configured to frequency divide the oscillating output signal to generate the feedback clock signal.