US 12,273,109 B2
Semiconductor integrated circuit
Jun Koyama, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on May 15, 2024, as Appl. No. 18/664,387.
Application 18/664,387 is a continuation of application No. 18/136,924, filed on Apr. 20, 2023, granted, now 12,021,530.
Application 18/136,924 is a continuation of application No. 17/359,940, filed on Jun. 28, 2021, granted, now 11,677,384, issued on Jun. 13, 2023.
Application 17/359,940 is a continuation of application No. 15/986,920, filed on May 23, 2018, granted, now 11,177,792, issued on Nov. 16, 2021.
Application 15/986,920 is a continuation of application No. 14/670,536, filed on Mar. 27, 2015, abandoned.
Application 14/670,536 is a continuation of application No. 14/037,450, filed on Sep. 26, 2013, granted, now 8,995,174, issued on Mar. 31, 2015.
Application 14/037,450 is a continuation of application No. 13/196,250, filed on Aug. 2, 2011, granted, now 8,547,771, issued on Oct. 1, 2013.
Claims priority of application No. 2010-178167 (JP), filed on Aug. 6, 2010; and application No. 2011-108342 (JP), filed on May 13, 2011.
Prior Publication US 2024/0305277 A1, Sep. 12, 2024
Int. Cl. G11C 5/06 (2006.01); G11C 5/14 (2006.01); G11C 8/04 (2006.01); H01L 21/8258 (2006.01); H01L 27/06 (2006.01); H01L 27/088 (2006.01); H01L 27/12 (2006.01); H01L 29/04 (2006.01); H01L 29/786 (2006.01); H03K 3/012 (2006.01); H03K 3/037 (2006.01); H03K 19/00 (2006.01); H01L 21/8234 (2006.01)
CPC H03K 3/012 (2013.01) [G11C 5/147 (2013.01); G11C 8/04 (2013.01); H01L 21/8258 (2013.01); H01L 27/0629 (2013.01); H01L 27/088 (2013.01); H01L 27/1225 (2013.01); H01L 29/045 (2013.01); H01L 29/7869 (2013.01); H01L 29/78693 (2013.01); H03K 3/0372 (2013.01); H03K 3/0375 (2013.01); H03K 19/0008 (2013.01); H01L 21/823412 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a plurality of circuits, the plurality of circuits each comprising:
a first transistor comprising silicon in a channel formation region; and
a second transistor comprising an oxide semiconductor in a semiconductor layer where a channel formation region is formed,
wherein the semiconductor device comprises:
a first insulating layer;
a second insulating layer;
a first conductive layer;
a second conductive layer;
a third conductive layer; and
a fourth conductive layer; and
a power supply line,
wherein the first insulating layer is over a gate electrode of the first transistor,
wherein a gate electrode of the second transistor is over the first insulating layer,
wherein the semiconductor layer of the second transistor is over the gate electrode of the second transistor,
wherein the second insulating layer is over the semiconductor layer of the second transistor,
wherein the first conductive layer is over the second insulating layer and electrically connected to the semiconductor layer of the second transistor and one of a source and a drain of the first transistor,
wherein the second conductive layer is over the second insulating layer and electrically connected to the other of the source and the drain of the first transistor,
wherein the third conductive layer is in the same layer as the gate electrode of the second transistor and electrically connected to the other of the source and the drain of the first transistor and the second conductive layer,
wherein the fourth conductive layer is over the second insulating layer,
wherein the fourth conductive layer is electrically connected to the semiconductor layer of the second transistor,
wherein the power supply line is supplied with a power supply potential, and
wherein the fourth conductive layer and the power supply line are configured to form a capacitor.