US 12,273,104 B2
Methods and apparatus to convert analog voltages to delay signals
Sovan Ghosh, Bengaluru (IN); and Visvesvaraya Appala Pentakota, Bangalore (IN)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Feb. 28, 2023, as Appl. No. 18/115,657.
Prior Publication US 2024/0291484 A1, Aug. 29, 2024
Int. Cl. H03K 5/01 (2006.01); H03K 17/687 (2006.01); H03K 5/00 (2006.01); H03M 1/12 (2006.01)
CPC H03K 17/6872 (2013.01) [H03K 5/01 (2013.01); H03K 2005/00078 (2013.01); H03M 1/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus to convert a voltage to a delay signal, the apparatus comprising:
a first transistor having: a first gate configured to receive an analog voltage signal, a first source coupled to ground, and a first drain;
a second transistor having: a second gate configured to receive a first control signal, a second source coupled to the first drain of the first transistor, and a second drain;
a third transistor having: a third gate configured to receive a second control signal, a third source configured to receive a supply voltage, and a third drain coupled to the second drain in the second transistor via a first terminal;
a capacitor having: a positive terminal coupled to the first terminal, and a negative terminal coupled to ground;
a fourth transistor having: a fourth gate configured to receive a third control signal, a fourth source, and a fourth drain coupled to the first terminal;
a fifth transistor having: a fifth gate configured to receive a bias voltage, a fifth source coupled to ground, and a fifth drain coupled to the fourth source of the fourth transistor;
a sixth transistor having: a sixth gate, a sixth source coupled to ground, and a sixth drain coupled to the fourth source of the fourth transistor;
a seventh transistor having: a seventh gate coupled to the first terminal, a seventh source configured to receive the supply voltage, and a seventh drain coupled to the sixth gate of the sixth transistor via second terminal; and
an eighth transistor having: an eighth gate coupled to the first terminal, an eighth source coupled ground, and an eighth drain coupled to the second terminal.