US 12,272,945 B2
Method and apparatus for DV/DT controlled ramp-on in multi-semiconductor solid-state power controllers
Peter James Handy, Cheltenham (GB); Ian David Johnson, Thornbury (GB); and Nicholas George Tembe, Worcester (GB)
Assigned to GE AVIATION SYSTEMS LIMITED, Gloucestershire (GB)
Filed by GE AVIATION SYSTEMS LIMITED, Gloucestershire (GB)
Filed on Aug. 29, 2022, as Appl. No. 17/897,339.
Claims priority of application No. 21208643 (EP), filed on Nov. 16, 2021.
Prior Publication US 2023/0155373 A1, May 18, 2023
Int. Cl. H02H 9/04 (2006.01); H02H 9/00 (2006.01); H03K 17/0812 (2006.01)
CPC H02H 9/041 (2013.01) [H02H 9/005 (2013.01); H03K 17/0812 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for slew rate control of a multi-semiconductor solid state power controller (SSPC), the method comprising:
measuring, by at least one sensor, a rate-change of output voltage across a load of the multi-semiconductor SSPC having at least two switching semiconductors connected, and operable, in parallel;
comparing, by at least one amplifier, the rate-change of output voltage to a set rate-change of output voltage value to generate a rate-change of voltage error signal;
receiving, by at least one controller, a current limit set point signal; and
determining a current setting signal based on at least the rate-change of voltage error signal and the current limit set point signal.