| CPC H01L 29/42392 (2013.01) [H01L 21/02359 (2013.01); H01L 29/401 (2013.01); H01L 29/66545 (2013.01); H01L 29/7851 (2013.01); H01L 29/78696 (2013.01)] | 20 Claims |
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1. A semiconductor device structure, comprising:
a first gate spacer and a second gate spacer formed over a semiconductor substrate, longitudinally extending along a first direction, and separated from each other by a gate electrode layer;
a first insulating layer longitudinally extending along a second direction to pass through the gate electrode layer, the first gate spacer and the second gate spacer; and
a gate dielectric layer having a top surface covered by the gate electrode layer;
wherein a top width of the gate dielectric layer is less than a top width of the gate electrode layer,
wherein the first gate spacer, the second gate spacer, and the first insulating layer have a first hydrophobic surface, a second hydrophobic surface, and a third hydrophobic surface, respectively, and
wherein the first hydrophobic surface, the second hydrophobic surface, and the third hydrophobic surface are in direct contact with a first sidewall surface, a second sidewall surface, and a third sidewall surface of the gate electrode layer, respectively.
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