US 12,272,730 B2
Transistor level interconnection methodologies utilizing 3D interconnects
Javier A. DeLaCruz, San Jose, CA (US); and David Edward Fisch, Pleasanton, CA (US)
Assigned to Adeia Semiconductor Inc., San Jose, CA (US)
Filed by Adeia Semiconductor Inc., San Jose, CA (US)
Filed on Dec. 28, 2022, as Appl. No. 18/147,651.
Application 17/217,104 is a division of application No. 16/265,456, filed on Feb. 1, 2019, granted, now 10,991,804, issued on Apr. 27, 2021.
Application 18/147,651 is a continuation of application No. 17/217,104, filed on Mar. 30, 2021, granted, now 11,688,776.
Claims priority of provisional application 62/650,220, filed on Mar. 29, 2018.
Prior Publication US 2023/0138732 A1, May 4, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01)
CPC H01L 29/4175 (2013.01) [H01L 21/02532 (2013.01); H01L 21/76275 (2013.01); H01L 21/76283 (2013.01); H01L 23/538 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/66568 (2013.01); H01L 24/05 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/13016 (2013.01)] 6 Claims
OG exemplary drawing
 
1. An integrated circuit device, comprising:
a silicon layer having formed therein a source region and a drain region of a transistor;
a gate of the transistor and one or more interconnect layers formed over a top side of the silicon layer; and a conductive interconnect structure formed through one or more dielectric layers formed over a bottom side of the silicon layer opposite the top side, wherein one end of the conductive interconnect structure is electrically connected to a bottom surface of one of the source and drain regions through an Ohmic contact, and wherein the other end of the conductive interconnect structure comprises a terminal portion having an exposed surface configured for bonding to an external component, wherein the terminal portion of the conductive interconnect structure comprises a rigid conductive post extending below the one or more dielectric layers.