US 12,272,724 B2
Three-dimensional device structure including substrate-embedded integrated passive device and methods for making the same
Jen-Yuan Chang, Hsinchu (TW); Chien-Chang Lee, Miaoli County (TW); Chia-Ping Lai, Hsinchu (TW); and Tzu-Chung Tsai, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Aug. 2, 2023, as Appl. No. 18/229,612.
Application 18/229,612 is a division of application No. 17/446,053, filed on Aug. 26, 2021, granted, now 11,855,130.
Prior Publication US 2023/0378247 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/00 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01); H01L 49/02 (2006.01)
CPC H01L 28/90 (2013.01) [H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 24/08 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 25/0657 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/09181 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/33181 (2013.01); H01L 2225/06541 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional device structure comprising a first die, wherein the first die comprises:
a first semiconductor substrate having a front side and an opposing back side;
a first interconnect structure disposed on the front side of the first semiconductor substrate;
a first through silicon via (TSV) structure that extends through the first semiconductor substrate and electrically contacts a metal feature of the first interconnect structure; and
an integrated passive device (IPD) embedded in the back side of the first semiconductor substrate and electrically connected to the first TSV structure.