US 12,272,714 B2
Solid-state imaging device
Kenji Kobayashi, Kanagawa (JP); Toshifumi Wakano, Kanagawa (JP); and Yusuke Otake, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed on Apr. 7, 2023, as Appl. No. 18/132,014.
Application 18/132,014 is a continuation of application No. 17/526,800, filed on Nov. 15, 2021, granted, now 11,699,716.
Application 17/526,800 is a continuation of application No. 16/803,787, filed on Feb. 27, 2020, granted, now 11,222,916, issued on Jan. 11, 2022.
Application 16/803,787 is a continuation of application No. 16/326,060, granted, now 10,680,028, issued on Jun. 9, 2020, previously published as PCT/JP2018/027845, filed on Jul. 25, 2018.
Claims priority of application No. 2017-151980 (JP), filed on Aug. 4, 2017.
Prior Publication US 2023/0246055 A1, Aug. 3, 2023
Int. Cl. H01L 27/146 (2006.01); H01L 23/522 (2006.01); H01L 31/107 (2006.01)
CPC H01L 27/14636 (2013.01) [H01L 23/5225 (2013.01); H01L 27/14603 (2013.01); H01L 27/14634 (2013.01); H01L 27/1464 (2013.01); H01L 31/107 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A light detecting device, comprising:
a semiconductor layer, including:
a first pixel, the first pixel including a first semiconductor region and a second semiconductor region; and
a second pixel, the second pixel including a third semiconductor region and a fourth semiconductor region;
a first wiring layer, including:
a first wiring;
a first via coupled to the first wiring and the first semiconductor region; and
a second via coupled to the first wiring and the third semiconductor region,
wherein, in a plan view, the first via is disposed between the second semiconductor region and the fourth semiconductor region, and
wherein, in the plan view, the second via is disposed between the second semiconductor region and the fourth semiconductor region;
a first chip, wherein the first chip includes the first and second pixels and the first wiring layer; and
a second chip, wherein the second chip is bonded to the first chip and includes circuitry for processing signals from the first and second pixels.
 
16. A light detecting device, comprising:
a semiconductor layer, including:
a first pixel, the first pixel including a first semiconductor region and a second semiconductor region; and
a second pixel, the second pixel including a third semiconductor region and a fourth semiconductor region;
a first wiring layer including:
a first wiring;
a first via coupled to the first wiring and the first semiconductor region; and
a second via coupled to the first wiring and the third semiconductor region,
wherein, in a plan view, the first wiring is disposed between the second semiconductor region and the fourth semiconductor region;
a first chip, wherein the first chip includes the first and second pixels and the first wiring layer; and
a second chip, wherein the second chip is bonded to the first chip and includes circuitry for processing signals from the first and second pixels.
 
20. A light detecting device, comprising:
a semiconductor layer, including:
a first pixel, the first pixel including a first semiconductor region and a second semiconductor region; and
a second pixel, the second pixel including a third semiconductor region and a fourth semiconductor region; and
a first wiring layer, including:
a first wiring;
a first via coupled to the first wiring and the first semiconductor region; and
a second via coupled to the first wiring and the third semiconductor region,
wherein, in a plan view, the first via is disposed between the second semiconductor region and the fourth semiconductor region, and
wherein, in the plan view, the second via is disposed between the second semiconductor region and the fourth semiconductor region;
a third wiring;
a second semiconductor region wiring between the third wiring and the second semiconductor region in a cross-sectional view, wherein the second semiconductor region wiring is coupled to the third wiring; and
a plurality of vias coupled to the second semiconductor region and the second semiconductor region wiring.