US 12,272,703 B2
Solid-state imaging element and solid-state imaging element manufacturing method
Susumu Tonegawa, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 17/618,562
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed May 19, 2020, PCT No. PCT/JP2020/019711
§ 371(c)(1), (2) Date Dec. 13, 2021,
PCT Pub. No. WO2020/261817, PCT Pub. Date Dec. 30, 2020.
Claims priority of application No. 2019-116867 (JP), filed on Jun. 25, 2019.
Prior Publication US 2022/0246653 A1, Aug. 4, 2022
Int. Cl. H01L 27/146 (2006.01); H01L 49/02 (2006.01)
CPC H01L 27/14612 (2013.01) [H01L 27/14636 (2013.01); H01L 27/1464 (2013.01); H01L 27/14689 (2013.01); H01L 28/90 (2013.01)] 33 Claims
OG exemplary drawing
 
1. A solid-state imaging element, comprising:
a semiconductor substrate that includes a photodiode (PD) configured to photoelectrically convert incident light and a floating diffusion (FD) to which a signal charge accumulated in the PD is transferred;
a capacitor that includes a PD side electrode disposed on a surface of the PD on a side opposite to a surface into which the light enters, and an opposite PD side electrode facing the PD side electrode with a dielectric film interposed between the PD side electrode and the opposite PD side electrode;
an amplification transistor that reads, as an electric signal, the signal charge transferred to the FD and amplifies the signal charge; and
an FD side wiring electrode that connects the FD and the amplification transistor,
wherein at least a part of the PD side electrode and the FD side wiring electrode are formed in the semiconductor substrate in such a shape as to extend in a thickness direction of the semiconductor substrate,
wherein one end of a first contact hole in which at least a part of the PD side electrode is formed and one end of a second contact hole in which the FD side wiring electrode is formed are both positioned in a surface of the semiconductor substrate on a side opposite to a PD side,
wherein the semiconductor substrate includes:
a first semiconductor substrate where a pixel circuit including the PD and the FD is disposed; and
a second semiconductor substrate laminated on a surface of the first semiconductor substrate on the side opposite to the PD side, and
wherein the capacitor includes:
a first capacitor portion formed in a first capacitor region defined in the first semiconductor substrate; and
a second capacitor portion disposed on a surface of the first capacitor portion on the side opposite to the PD side.