US 12,272,690 B2
Gate isolation for multigate device
Shi Ning Ju, Hsinchu (TW); Zhi-Chang Lin, Zhubei (TW); Shih-Cheng Chen, Taipei (TW); Chih-Hao Wang, Hsinchu County (TW); Kuo-Cheng Chiang, Hsinchu County (TW); and Kuan-Ting Pan, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Mar. 27, 2023, as Appl. No. 18/190,657.
Application 18/190,657 is a continuation of application No. 17/170,740, filed on Feb. 8, 2021, granted, now 11,616,062.
Claims priority of provisional application 63/018,188, filed on Apr. 30, 2020.
Prior Publication US 2023/0260998 A1, Aug. 17, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/092 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/092 (2013.01) [H01L 21/02603 (2013.01); H01L 21/28123 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823828 (2013.01); H01L 21/823878 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming an isolation feature over a substrate, wherein the isolation feature is disposed between a first fin portion and a second fin portion extending from the substrate;
forming a dielectric gate isolation fin over the isolation feature, wherein the dielectric gate isolation fin includes a dielectric feature having an oxide layer disposed over a low-k dielectric layer and a high-k dielectric layer disposed over the dielectric feature;
forming a gate dielectric layer over a first semiconductor layer, a second semiconductor layer, the dielectric gate isolation fin, and the isolation feature, wherein the first semiconductor layer is disposed over the first fin portion, the second semiconductor layer is disposed over the second fin portion, and the gate dielectric layer wraps the first semiconductor layer, the second semiconductor layer, and the dielectric gate isolation fin;
forming a gate electrode layer over the gate dielectric layer, wherein the gate electrode layer wraps the first semiconductor layer, the second semiconductor layer, and the dielectric gate isolation fin; and
etching back the gate electrode layer to a depth below a top surface of the dielectric gate isolation fin, such that the dielectric gate isolation fin is disposed between a first remainder of the gate electrode layer that wraps the first semiconductor layer and a second remainder of the gate electrode layer that wraps the second semiconductor layer.