US 12,272,678 B2
Semiconductor package and manufacturing method thereof
Jie Chen, New Taipei (TW); and Hsien-Wei Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 12, 2023, as Appl. No. 18/351,471.
Application 18/351,471 is a continuation of application No. 17/378,790, filed on Jul. 19, 2021, granted, now 11,749,651.
Application 17/378,790 is a continuation of application No. 16/882,517, filed on May 24, 2020, granted, now 11,069,662, issued on Jul. 20, 2021.
Application 16/882,517 is a continuation of application No. 16/103,939, filed on Aug. 15, 2018, granted, now 10,665,572, issued on May 26, 2020.
Prior Publication US 2023/0369295 A1, Nov. 16, 2023
Int. Cl. H01L 25/07 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/072 (2013.01) [H01L 23/3114 (2013.01); H01L 23/3121 (2013.01); H01L 23/5384 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 24/73 (2013.01); H01L 25/50 (2013.01); H01L 2224/0401 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first semiconductor die and a second semiconductor die, encapsulated in a first insulating encapsulation; and
a first chip package, located on and electrically coupled to the first semiconductor die and the second semiconductor die, wherein the first chip package extends from the first semiconductor die to the second semiconductor die and comprises:
third semiconductor dies, located on a substrate;
an interconnect, located on and electrically coupled to the third semiconductor dies; and
a first insulating encapsulant, encapsulating the third semiconductor dies and located between the substrate and the first insulating encapsulation, wherein a sidewall of the substrate is substantially aligned with a sidewall of the interconnect,
wherein along a stacking direction of the first chip package and the first semiconductor die, a projection of the first semiconductor die and a projection of the second semiconductor die are extended beyond a projection of the first chip package.