US 12,272,677 B2
Direct bonded stack structures for increased reliability and improved yield in microelectronics
Cyprian Emeka Uzoh, San Jose, CA (US); Rajesh Katkar, Milpitas, CA (US); Thomas Workman, San Jose, CA (US); Guilian Gao, San Jose, CA (US); Gaius Gillman Fountain, Jr., Youngsville, NC (US); Laura Wills Mirkarimi, Sunol, CA (US); Belgacem Haba, Saratoga, CA (US); Gabriel Z. Guevara, San Jose, CA (US); and Joy Watanabe, Campbell, CA (US)
Assigned to ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC., San Jose, CA (US)
Filed by ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC., San Jose, CA (US)
Filed on Feb. 27, 2024, as Appl. No. 18/589,231.
Application 18/589,231 is a continuation of application No. 17/681,563, filed on Feb. 25, 2022.
Application 17/681,563 is a continuation of application No. 16/911,360, filed on Jun. 24, 2020, granted, now 11,296,053, issued on Apr. 5, 2022.
Claims priority of provisional application 62/866,965, filed on Jun. 26, 2019.
Prior Publication US 2024/0203948 A1, Jun. 20, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2023.01)
CPC H01L 25/0657 (2013.01) [H01L 21/561 (2013.01); H01L 23/3121 (2013.01); H01L 24/97 (2013.01); H01L 2224/0401 (2013.01); H01L 2924/3511 (2013.01); H01L 2924/35121 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a substrate;
a die stack on the substrate, the die stack comprising a plurality of dies including:
a first integrated device die comprising a first integrated circuit;
a second integrated device die comprising a second integrated circuit, the first integrated device die hybrid bonded to a first bonding layer on the second integrated device die; and
a dummy die directly bonded to a second bonding layer on an underlying die of the die stack without an intervening adhesive;
a first lateral die support layer disposed along at least a portion of a sidewall of the first integrated device die, an entirety of the first lateral die support layer disposed laterally outside a footprint of the first integrated device die, the first lateral die support layer having a laterally outermost side surface; and
a second lateral die support layer disposed on the substrate and adjacent the laterally outermost side surface of the first lateral die support layer, the second lateral die support layer covering an entirety of the laterally outermost side surface of the first lateral die support layer.