US 12,272,675 B2
Method of forming 3D stacked compute and memory with copper pillars
Sasikanth Manipatruni, Portland, OR (US); Rajeev Kumar Dokania, Beaverton, OR (US); Amrita Mathuriya, Portland, OR (US); and Ramamoorthy Ramesh, Moraga, CA (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Jul. 25, 2023, as Appl. No. 18/358,552.
Application 18/358,552 is a continuation of application No. 17/472,325, filed on Sep. 10, 2021, granted, now 11,764,190.
Application 17/472,325 is a continuation of application No. 16/357,265, filed on Mar. 18, 2019, granted, now 11,139,270, issued on Oct. 5, 2021.
Prior Publication US 2024/0047426 A1, Feb. 8, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); G06F 9/50 (2006.01); G11C 7/10 (2006.01); G11C 11/419 (2006.01); H01L 23/00 (2006.01); H01L 23/525 (2006.01); H10B 10/00 (2023.01)
CPC H01L 25/0657 (2013.01) [G06F 9/5077 (2013.01); G11C 7/1006 (2013.01); G11C 11/419 (2013.01); H01L 23/525 (2013.01); H01L 24/73 (2013.01); H10B 10/00 (2023.02); H01L 2224/32145 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A method comprising:
forming a substrate having a top surface;
forming a first die directly on the top surface of the substrate through bumps or vias, wherein the first die comprises a ferroelectric random-access memory (FeRAM) having bit-cells, wherein each bit-cell comprises an access transistor and a capacitor including ferroelectric material, and wherein the access transistor is coupled to the ferroelectric material;
forming a second die vertically stacked over the first die, wherein the second die comprises a computational logic including an array of multiplier cells, and wherein the computational logic is coupled to the FeRAM of the first die;
forming a first silicon structure adjacent to the second die but not vertically stacked with the second die, wherein the first silicon structure comprises first active and/or passive devices; and
forming a second silicon structure adjacent to the second die but not vertically stacked with the second die, wherein the first silicon structure and the second silicon structure are on either side of the second die, wherein the second silicon structure comprises second active and/or passive devices;
wherein:
the first die has a first surface;
the second die has a second surface;
the first surface is to face the second surface such that the first surface is to substantially overlap the second surface or the second surface is to substantially overlap the first surface; and
the first die and the second die are connected via inter-die copper pillars which are not solder bumps, wherein the first die includes first through-silicon vias, and wherein the second die includes second through-silicon vias.