US 12,272,674 B2
Stacking structure, package structure and method of fabricating the same
Ming-Fa Chen, Taichung (TW); Sung-Feng Yeh, Taipei (TW); Tzuan-Horng Liu, Taoyuan (TW); and Chao-Wen Shih, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 23, 2023, as Appl. No. 18/357,137.
Application 18/357,137 is a continuation of application No. 17/406,120, filed on Aug. 19, 2021, granted, now 11,784,163.
Application 17/406,120 is a continuation of application No. 16/581,795, filed on Sep. 25, 2019, granted, now 11,114,413, issued on Sep. 7, 2021.
Claims priority of provisional application 62/867,241, filed on Jun. 27, 2019.
Prior Publication US 2023/0361086 A1, Nov. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01)
CPC H01L 25/0657 (2013.01) [H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 21/78 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/83 (2013.01); H01L 24/85 (2013.01); H01L 24/89 (2013.01); H01L 24/92 (2013.01); H01L 24/97 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48228 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/80006 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/83005 (2013.01); H01L 2224/85005 (2013.01); H01L 2224/92247 (2013.01); H01L 2224/95001 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/06593 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a first stacked die unit, comprising:
providing a semiconductor wafer having a base semiconductor die, wherein the base semiconductor die includes a plurality of first bonding pads;
stacking a first bonding chip on the base semiconductor die, wherein the first bonding chip includes a plurality of first bonding structures, and the first bonding chip is stacked on the base semiconductor die in a way that two or more of the plurality of first bonding pads are joined with one of the plurality of first bonding structures;
dicing the semiconductor wafer to separate out the base semiconductor die and the first bonding chip to form the first stacked die unit; and
forming a second stacked die unit on the first stacked die unit, wherein the second stacked die unit comprises a second base die and a second chip stacked on the second base die.