US 12,272,671 B2
Semiconductor device package and method for manufacturing the same
Chih-Ming Hung, Kaohsiung (TW); Meng-Jen Wang, Kaohsiung (TW); Tsung-Yueh Tsai, Kaohsiung (TW); and Jen-Kai Ou, Kaohsiung (TW)
Assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC., Kaohsiung (TW)
Filed by Advanced Semiconductor Engineering, Inc., Kaohsiung (TW)
Filed on Jun. 20, 2023, as Appl. No. 18/212,158.
Application 18/212,158 is a continuation of application No. 17/180,364, filed on Feb. 19, 2021, granted, now 11,682,653.
Application 17/180,364 is a continuation of application No. 16/709,623, filed on Dec. 10, 2019, granted, now 10,937,761, issued on Mar. 2, 2021.
Application 16/709,623 is a continuation of application No. 15/918,906, filed on Mar. 12, 2018, granted, now 10,522,505, issued on Dec. 31, 2019.
Claims priority of provisional application 62/482,431, filed on Apr. 6, 2017.
Prior Publication US 2023/0335533 A1, Oct. 19, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/544 (2006.01); H01L 27/146 (2006.01); G06V 40/13 (2022.01)
CPC H01L 24/96 (2013.01) [H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 23/31 (2013.01); H01L 23/3107 (2013.01); H01L 23/3121 (2013.01); H01L 23/315 (2013.01); H01L 23/544 (2013.01); H01L 24/13 (2013.01); H01L 27/14618 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 27/1469 (2013.01); G06V 40/1318 (2022.01); G06V 40/1329 (2022.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54486 (2013.01); H01L 2224/13014 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/1319 (2013.01); H01L 2224/13583 (2013.01); H01L 2224/13611 (2013.01); H01L 2224/13639 (2013.01); H01L 2224/13644 (2013.01); H01L 2224/13647 (2013.01); H01L 2224/13655 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/95001 (2013.01); H01L 2924/014 (2013.01); H01L 2924/15321 (2013.01); H01L 2924/181 (2013.01); H01L 2924/19105 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a circuit structure having a first surface and a second surface opposite to the first surface;
a sensing element disposed adjacent to the second surface of the circuit structure;
a first encapsulant covering the second surface of the circuit structure, wherein the sensing element has a surface completely in contact with the first encapsulant;
a second encapsulant covering the first surface of the circuit structure; and
a passive component disposed adjacent to the first surface of the circuit structure,
wherein the first encapsulant has a top surface adjacent to the first surface and a bottom surface adjacent to the second surface of the circuit structure, and the top surface of the first encapsulant is at an elevation, with respect to the circuit structure, higher than that of a top surface of the passive component.