US 12,272,670 B2
Integrated semiconductor packaging system with enhanced dielectric-to-dielectric bonding quality
Jen-Yuan Chang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 15, 2022, as Appl. No. 17/819,639.
Prior Publication US 2024/0055389 A1, Feb. 15, 2024
Int. Cl. H01L 21/00 (2006.01); H01L 21/02 (2006.01); H01L 21/67 (2006.01); H01L 23/00 (2006.01)
CPC H01L 24/80 (2013.01) [H01L 21/02052 (2013.01); H01L 21/6704 (2013.01); H01L 21/67173 (2013.01); H01L 24/08 (2013.01); H01L 24/74 (2013.01); H01L 24/94 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/94 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated semiconductor packaging system comprising:
a first wet clean tool configured to perform a first wet clean process on a frame, wherein a plurality of top dies are disposed on the frame;
a second wet clean tool configured to perform a second wet clean process on a wafer, wherein a plurality of bottom dies corresponding to the plurality of top dies, respectively, are disposed on the wafer;
a pick-and-place tool configured to bond the plurality of top dies to the plurality of bottom dies, respectively; and
a first transmission path through which the frame and the wafer are transferred from the first wet clean tool and the second wet clean tool to the pick-and-place tool, respectively, wherein the frame is directly transferred from the first wet clean tool to the pick-and-place tool, and the wafer is directly transferred from the second wet clean tool to the pick-and-place tool.