US 12,272,666 B2
Semiconductor package and method of manufacturing the same
Eunsil Kim, Cheonan-si (KR); Seunghan Sim, Incheon (KR); and Gun Lee, Yongin-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 16, 2022, as Appl. No. 17/745,612.
Claims priority of application No. 10-2021-0102667 (KR), filed on Aug. 4, 2021.
Prior Publication US 2023/0045383 A1, Feb. 9, 2023
Int. Cl. H01L 23/00 (2006.01)
CPC H01L 24/20 (2013.01) [H01L 24/19 (2013.01); H01L 2224/2101 (2013.01); H01L 2224/2105 (2013.01); H01L 2224/211 (2013.01); H01L 2224/214 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor package, the method comprising:
forming an insulating layer on a semiconductor chip;
forming a via pattern hole in the insulating layer by etching at least a portion of the insulating layer, the via pattern hole exposing at least a portion of the semiconductor chip;
forming a seed layer on the insulating layer and on the portion of the semiconductor chip exposed in the via pattern hole;
forming a photoresist layer on the seed layer;
exposing the photoresist layer such that an amount of hardening of a middle portion of the photoresist layer is greater than an amount of hardening of an upper portion of the photoresist layer and an amount of hardening of a lower portion of the photoresist layer;
forming a photoresist pattern having a plurality of line pattern holes by developing the photoresist layer; and
forming a redistribution pattern by filling the via pattern hole of the insulating layer and the plurality of line pattern holes of the photoresist pattern.