US 12,272,661 B2
Semiconductor package including semiconductor chips stacked via conductive bumps
Eunsu Lee, Asan-si (KR); Dongho Kim, Asan-si (KR); Jiyong Park, Asan-si (KR); and Jeonghyun Lee, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 29, 2021, as Appl. No. 17/564,689.
Claims priority of application No. 10-2021-0058387 (KR), filed on May 6, 2021.
Prior Publication US 2022/0359439 A1, Nov. 10, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/06 (2013.01) [H01L 23/481 (2013.01); H01L 24/16 (2013.01); H01L 25/0657 (2013.01); H01L 2224/0605 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/06515 (2013.01); H01L 2224/16146 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first semiconductor chip including a first substrate having a first surface and a second surface opposite each other, a first bonding pad on the first surface of the first substrate, a first through electrode penetrating through the first substrate and being electrically connected to the first bonding pad, and a second bonding pad in a first recess of the first substrate,
the first recess being recessed from the second surface of the first substrate to a depth in the first substrate and exposing an end portion of the first through electrode through a bottom of the first recess,
the second bonding pad being in the first recess and electrically connected to the first through electrode;
a second semiconductor chip stacked on the second surface of the first substrate, the second semiconductor chip including a second substrate having a third surface and a fourth surface opposite to each other and a third bonding pad on the third surface; and
a conductive connection member between the second bonding pad and the third bonding pad, at least a portion of the conductive connection member being in the first recess.