US 12,272,650 B2
Microelectronic package with substrate cavity for bridge-attach
Omkar G. Karhade, Chandler, AZ (US); Debendra Mallik, Chandler, AZ (US); Nitin A. Deshpande, Chandler, AZ (US); and Amruthavalli Pallavi Alur, Tempe, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 28, 2020, as Appl. No. 16/804,835.
Prior Publication US 2021/0272905 A1, Sep. 2, 2021
Int. Cl. H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/13 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01)
CPC H01L 23/5381 (2013.01) [H01L 23/13 (2013.01); H01L 23/49816 (2013.01); H01L 23/5226 (2013.01); H01L 24/13 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A microelectronic package comprising:
a substrate with a cavity therein, wherein the substrate comprises a plurality of layers;
a component positioned within the substrate, wherein the component is exposed by the cavity through the plurality of layers;
a bridge die physically and communicatively coupled with the component by an interconnect including a solder bump, within the cavity, coupled to the component and to the bridge die, wherein the bridge die is to facilitate transmission of an electronic signal between the component and a second component to which the bridge die is coupled, and wherein the bridge die is not within the cavity; and
a metal pad partially within the cavity, wherein the metal pad is physically and communicatively coupled with the bridge, wherein:
the solder bump is physically and communicatively coupled with the metal pad and the component; and
the solder bump is between the metal pad and the component.