| CPC H01L 23/5286 (2013.01) [H10D 30/6219 (2025.01); H10D 84/0186 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01)] | 19 Claims |
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1. A semiconductor device comprising:
a plurality of field effect transistors (FET) formed upon semiconductor fins, wherein each FET comprises a gate disposed transversely upon a first portion of the semiconductor fins of the FET, one or more source/drain regions disposed upon the semiconductor fins and in contact with the gate, and an electrically isolating layer disposed adjacent to a second portion of the semiconductor fins above the gate and the source/drain regions, the electrically isolating layer having an interface with the gate;
a buried power rail (BPR) disposed between otherwise adjacent FETs, the BPR comprising a metal rail extending beyond the interface into the gate, and electrically isolating sidewalls separating the metal rail from the gate and the source/drain regions;
and a via-buried power rail contact disposed adjacent to the electrically isolating sidewalls, in contact with the metal rail, and in contact with one source/drain region.
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