US 12,272,647 B2
3D stacked chip that shares power rails
Byounghak Hong, Albany, NY (US); Kang-ill Seo, Albany, NY (US); and Jason Martineau, Fremont, CA (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 14, 2022, as Appl. No. 17/720,642.
Claims priority of provisional application 63/308,692, filed on Feb. 10, 2022.
Prior Publication US 2023/0253324 A1, Aug. 10, 2023
Int. Cl. H01L 23/528 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/5286 (2013.01) [H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A three-dimensionally (3D) stacked semiconductor chip architecture comprising:
a first semiconductor chip comprising:
a first semiconductor layer;
a first front-end-of-line (FEOL) layer provided on a first side of the first semiconductor layer;
a first middle-of-line (MOL) layer provided on the first FEOL layer;
a first back-end-of-line (BEOL) layer provided on the first MOL layer;
a first power rail layer provided on a second side of the first semiconductor layer;
a second semiconductor chip comprising:
a second semiconductor layer;
a second FEOL layer provided on a first side of the second semiconductor layer;
a second MOL layer provided on the second FEOL layer;
a second BEOL layer provided on the second MOL layer;
a second power rail layer provided on a second side of the second semiconductor layer,
wherein the first power rail layer and the second power rail layer contact each other,
wherein the first power rail layer comprises a first power rail configured to distribute power, and the second power rail layer comprises a second power rail configured to distribute power, and
wherein an entirety of the first power rail is parallel to an entirety of the second power rail.