US 12,272,646 B2
Semiconductor memory device
Feng-Yi Chang, Tainan (TW); Shih-Fang Tzou, Tainan (TW); Fu-Che Lee, Taichung (TW); Chien-Cheng Tsai, Kaohsiung (TW); and Feng-Ming Huang, Pingtung County (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW); and Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou (CN)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW); and Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou (CN)
Filed on Jul. 26, 2023, as Appl. No. 18/226,750.
Application 18/226,750 is a division of application No. 17/467,287, filed on Sep. 6, 2021, granted, now 11,769,727.
Application 16/446,590 is a division of application No. 15/856,089, filed on Dec. 28, 2017, granted, now 10,381,306, issued on Aug. 13, 2019.
Application 17/467,287 is a continuation of application No. 16/446,590, filed on Jun. 19, 2019, granted, now 11,139,243, issued on Oct. 5, 2021.
Claims priority of application No. 201611258003.0 (CN), filed on Dec. 30, 2016.
Prior Publication US 2023/0369215 A1, Nov. 16, 2023
Int. Cl. H01L 23/52 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H10B 12/00 (2023.01)
CPC H01L 23/5283 (2013.01) [H01L 21/31111 (2013.01); H01L 21/76224 (2013.01); H01L 21/76802 (2013.01); H01L 21/76831 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 29/0649 (2013.01); H10B 12/482 (2023.02); H10B 12/485 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a semiconductor substrate comprising a plurality of active regions;
a plurality of shallow trench isolations disposed in the semiconductor substrate, wherein each of the plurality of shallow trench isolation is disposed between the plurality of active regions;
a bit line contact opening disposed in one of the plurality of active regions and disposed in the plurality of shallow trench isolations, wherein an edge of the bit line contact opening has an under-cut structure;
a bit line structure partially disposed in the bit line contact opening and in contact with the one of the plurality of active regions corresponding to the bit line contact opening;
an isolation structure disposed in the under-cut structure of the bit line contact opening, wherein a distance between a sidewall of the bit line structure and a topmost portion of an outermost sidewall of the under-cut structure is less than a distance between the sidewall of the bit line structure and a bottommost portion of the outermost sidewall of the under-cut structure; and
a spacer layer, wherein a portion of the spacer layer is disposed between the isolation structure and the bit line structure, and a bottom surface of the portion of the spacer layer disposed between the isolation structure and the bit line structure is lower than a top surface of the one of the plurality of active regions corresponding to the bit line contact opening,
wherein a bottom surface and a side surface of the under-cut structure comprises a curved surface, and the curved surface is lower than the top surface of the one of the plurality of active regions corresponding to the bit line contact opening;
wherein a bottom surface and a side surface of the isolation structure comprises the curved surface, and the curved surface of the bottom surface of the isolation structure is lower than the top surface of the one of the plurality of active regions corresponding to the bit line contact opening.