US 12,272,645 B2
Three-dimensional memory devices and fabricating methods thereof
Lei Liu, Hubei (CN); Yuancheng Yang, Hubei (CN); Wenxi Zhou, Hubei (CN); Kun Zhang, Hubei (CN); Di Wang, Hubei (CN); Tao Yang, Hubei (CN); Dongxue Zhao, Hubei (CN); Zhiliang Xia, Hubei (CN); and Zongliang Huo, Hubei (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on May 6, 2022, as Appl. No. 17/738,786.
Prior Publication US 2023/0361031 A1, Nov. 9, 2023
Int. Cl. H10B 12/00 (2023.01); H01L 23/528 (2006.01); H10B 41/20 (2023.01); H10B 43/20 (2023.01)
CPC H01L 23/5283 (2013.01) [H10B 41/20 (2023.02); H10B 43/20 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A method for forming a memory structure, comprising:
forming a bottom conductive layer on a substrate;
forming a dielectric stack on the bottom conductive layer, the dielectric stack comprising a plurality of alternatively arranged first dielectric layers and second dielectric layers;
forming an opening penetrating the dielectric stack and exposing the bottom conductive layer;
forming a cap layer on a bottom of the opening;
forming a cylindrical body and a top contact on the cap layer and in the opening;
forming a gate line slit penetrating the dielectric stack; and
replacing the plurality of second dielectric layers with conductive layers by:
removing the plurality of second dielectric layers through the gate line slit to form a plurality of horizontal trenches; and
forming the conductive layers in the plurality of horizontal trenches.