US 12,272,642 B2
Benchmark device on a semiconductor wafer with fuse element
Yi-Ju Chen, Taipei (TW); and Jui-Hsiu Jao, Taoyuan (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Oct. 13, 2021, as Appl. No. 17/499,911.
Prior Publication US 2023/0116600 A1, Apr. 13, 2023
Int. Cl. H01L 23/525 (2006.01); H01L 21/66 (2006.01); H10D 89/60 (2025.01)
CPC H01L 23/5256 (2013.01) [H01L 22/14 (2013.01); H10D 89/921 (2025.01); H10D 89/611 (2025.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor wafer, comprising:
a benchmark device disposed within a scribe line of the semiconductor wafer; the benchmark device comprising:
a transistor comprising a bulk electrode;
a diode comprising an anode electrode receiving a test signal from a signal generator, wherein the anode electrode of the diode is not coupled to the bulk electrode of the transistor; and
a disconnecting switch electrically connected to the transistor and the diode, wherein the disconnecting switch is configured to form a conductive path between the transistor and the diode at a first stage, and to electrically isolate the transistor from the diode at a second stage.