US 12,272,641 B2
Semiconductor structure, memory and method for operating memory
Yanzhe Tang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 23, 2022, as Appl. No. 17/951,213.
Application 17/951,213 is a continuation of application No. PCT/CN2022/109589, filed on Aug. 2, 2022.
Claims priority of application No. 202210806749.X (CN), filed on Jul. 8, 2022.
Prior Publication US 2023/0035348 A1, Feb. 2, 2023
Int. Cl. H01L 23/525 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); H10B 20/25 (2023.01)
CPC H01L 23/5252 (2013.01) [G11C 17/16 (2013.01); G11C 17/18 (2013.01); H10B 20/25 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a first gate structure and a second gate structure that are located on a surface of the substrate and have a same thickness; and
a first doped area and a second doped area that are located in the substrate and are located on two sides of the first gate structure respectively, wherein the first gate structure forms a selection transistor with the first doped area and the second doped area;
an orthographic projection of the second gate structure on the substrate is at least partially overlapped with the second doped area; the second gate structure and the second doped area form an antifuse bit structure; and a breakdown state and a non-breakdown state of the antifuse bit structure are configured to represent different stored data respectively;
a first metal line wherein the first metal line is located above the first gate structure and the second gate structure, and is connected with the first doped area through a first connection structure; and
a second metal line, wherein the ta line the first gate structure and the first metal line, and is connected with the substrate through a second connection structure.