US 12,272,639 B2
Integrated inductor with inductor wire formed in an integrated circuit layer stack
Yaojian Leng, Vancouver, WA (US)
Assigned to Microchip Technology Incorporated, Chandler, AZ (US)
Filed by Microchip Technology Incorporated, Chandler, AZ (US)
Filed on Apr. 13, 2022, as Appl. No. 17/719,548.
Claims priority of provisional application 63/272,513, filed on Oct. 27, 2021.
Prior Publication US 2023/0129684 A1, Apr. 27, 2023
Int. Cl. H01L 23/52 (2006.01); H01F 17/00 (2006.01); H01F 27/28 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H10D 1/20 (2025.01)
CPC H01L 23/5227 (2013.01) [H01F 17/0013 (2013.01); H01F 27/2823 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H10D 1/20 (2025.01); H01F 2017/002 (2013.01); H01F 2017/0073 (2013.01); H01F 2017/0086 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
an integrated circuit (IC) layer stack including multiple metal layers and multiple via layers formed in an alternating manner in a vertical direction, with respective via layers located between a respective pair of the metal layers;
an integrated inductor comprising an inductor wire including multiple wire loops,
wherein a respective wire loop of the multiple wire loops includes (a) a laterally-extending lower wire segment formed in a lower metal layer in the IC layer stack, (b) a laterally-extending upper wire segment formed in an upper metal layer in the IC layer stack, (c) a pair of vertically-extending side wire segments connected between the laterally-extending lower wire segment and the laterally-extending upper wire segment;
wherein each vertically-extending side wire segment is defined by a multi-layer inductor element stack including:
multiple metal layer inductor elements formed in multiple respective metal layers in the IC layer stack between the lower metal layer and the upper metal layer; and
multiple via layer inductor elements formed in multiple respective via layers in the IC layer stack, wherein the multiple metal layer inductor elements and the multiple via layer inductor elements are conductively connected to each other;
wherein the multiple via layer inductor elements each have a length of at least 1 μm in each of two lateral directions orthogonal to each other and perpendicular to the vertical direction; and
a metal interconnect arrangement including:
respective metal layer interconnect elements formed in the multiple respective metal layers; and
respective interconnect vias formed in the multiple respective via layers.