| CPC H01L 23/5226 (2013.01) [H01L 23/5283 (2013.01); H10B 41/27 (2023.02); H10B 41/30 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/27 (2023.02); H10B 43/30 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10B 63/84 (2023.02)] | 13 Claims |

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1. A method of manufacturing a semiconductor device, the method comprising:
forming a stack structure in which a plurality of interlayer insulating layers and a plurality of sacrificial layers are stacked in an alternating manner;
simultaneously forming first holes to form contact plugs that penetrate the stack structure and second holes to form support structures by etching the stack structure;
forming contact plugs by filling the first holes with a barrier layer and a conductive layer for gates;
simultaneously filling the second holes with the barrier layer and the conductive layer for gates while filling the first holes;
forming, on the top of the stack structure, a mask pattern including first openings through which a region of the second holes is exposed;
removing the conductive layer for gates in the second holes by performing a first etching process by using the mask pattern; and
forming support structures by filling the second holes with an insulating layer.
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