	US 12,272,634 B2
	Semiconductor structure having an anchor-shaped backside via
Chun-Yuan Chen, Hsinchu (TW); Huan-Chieh Su, Changhua County (TW); Cheng-Chi Chuang, New Taipei (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 17, 2023, as Appl. No. 18/301,757.
Application 17/582,314 is a division of application No. 16/926,447, filed on Jul. 10, 2020, granted, now 11,233,005.
Application 18/301,757 is a continuation of application No. 17/582,314, filed on Jan. 24, 2022, granted, now 11,631,638.
Prior Publication US 2023/0260897 A1, Aug. 17, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 23/528 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)

CPC H01L 23/5226 (2013.01) [H01L 21/76897 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 23/5283 (2013.01); H01L 23/5286 (2013.01); H01L 27/0886 (2013.01); H01L 29/0653 (2013.01); H01L 29/4175 (2013.01); H01L 29/41766 (2013.01); H01L 29/41791 (2013.01); H01L 29/42392 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01)]

20 Claims

1. A semiconductor structure, comprising:

a source/drain (S/D) region;

one or more dielectric layers over the S/D region;

one or more semiconductor channel layers connected to the S/D region;

an isolation structure under the S/D region and the one or more semiconductor channel layers; and

a via under the S/D region and electrically connected to the S/D region, wherein a lower portion of the via is surrounded by the isolation structure, and an upper portion of the via extends vertically between the S/D region and the isolation structure, wherein in a cross-section that extends through the S/D region and perpendicular to a lengthwise direction of the one or more semiconductor channel layers, the via has a shape of an anchor.

10. A semiconductor structure, comprising:

first and second source/drain (S/D) regions;

a first dielectric layer over the first and the second S/D regions;

a semiconductor channel layer connected to the first S/D region;

a second dielectric layer sandwiched between the first and the second S/D regions in a cross-section that extends through the first S/D region and perpendicular to a lengthwise direction of the semiconductor channel layer;

an isolation structure under the first and the second S/D regions and the semiconductor channel layer; and

a via under the first S/D region and electrically connected to the first S/D region, wherein an upper portion of the via extends vertically between the first S/D region and the isolation structure in the cross-section.

16. A semiconductor structure, comprising:

a source/drain (S/D) region;

a first dielectric layer over the S/D region;

a semiconductor channel layer connected to the S/D region;

a gate over the semiconductor channel layer;

an isolation structure under the S/D region, the semiconductor channel layer, and the gate;

a via under the S/D region, wherein an upper portion of the via extends vertically between the S/D region and the isolation structure;

a second dielectric layer vertically between the gate and a lower portion of the via;

a power rail under the isolation structure, wherein the via electrically connects the S/D region to the power rail; and

a dielectric fin on the isolation structure and adjacent the S/D region, wherein the upper portion of the via directly contacts the dielectric fin.