| CPC H01L 23/5223 (2013.01) [H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 23/53295 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/48 (2013.01); H01L 24/85 (2013.01); H01L 28/60 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/0557 (2013.01); H01L 2924/19041 (2013.01)] | 16 Claims |

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1. An integrated circuit with an isolation capacitor comprising:
a first conductive plate above a substrate;
a second conductive plate above the first conductive plate;
a first dielectric region between the first conductive plate and the second conductive plate;
a third conductive plate above the second conductive plate, the first conductive plate, the second conductive plate, and the third conductive plate being conductive plates of the isolation capacitor on the integrated circuit with no conductive metal path formed between the first conductive plate and the second conductive plate, the third conductive plate having a first perimeter being recessed from a second perimeter of the second conductive plate, a first thickness of the second conductive plate differing from a second thickness of the third conductive plate;
a second dielectric region between the second conductive plate and the third conductive plate, the third conductive plate being separated from the second conductive plate by a thickness of the second dielectric region, and a thickness of the first dielectric region differing from a thickness of the second dielectric region, the third conductive plate being off center from the second conductive plate in a first lateral direction, the first conductive plate being off center from the second conductive plate in a second lateral direction opposite the first lateral direction, and the first conductive plate being at least partially outside a perimeter of the third conductive plate; and
a plurality of conductive vias formed in the second dielectric region to electrically couple the second conductive plate and the third conductive plate.
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