US 12,272,630 B2
Interposer and semiconductor package including same
Ungcheon Kim, Cheonan-si (KR); Sungwoo Park, Seongnam-si (KR); Yukyung Park, Hwaseong-si (KR); and Seungkwan Ryu, Seongnam-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 5, 2023, as Appl. No. 18/347,519.
Application 18/347,519 is a continuation of application No. 17/154,067, filed on Jan. 21, 2021, granted, now 11,728,255.
Claims priority of application No. 10-2020-0084942 (KR), filed on Jul. 9, 2020.
Prior Publication US 2023/0352386 A1, Nov. 2, 2023
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 25/18 (2023.01)
CPC H01L 23/49822 (2013.01) [H01L 21/4857 (2013.01); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 25/18 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a package substrate;
an interposer mounted on the package substrate; and
a semiconductor chip mounted on the interposer,
wherein the interposer comprises
a base layer including a first surface and a second surface opposite the first surface,
a redistribution structure on the first surface of the base layer, configured to mount the semiconductor chip and including a conductive redistribution pattern,
a first lower protection layer on the second surface of the base layer,
a lower conductive pad on the first lower protection layer,
a through electrode passing through the base layer and the first lower protection layer to electrically connect the conductive redistribution pattern to the lower conductive pad,
a second lower protection layer on the first lower protection layer and contacting at least a portion of the lower conductive pad, and
an indentation formed in an outer edge region of the interposer to provide a continuous sidewall extending entirely through the second lower protection layer and entirely through the first lower protection layer to expose a linear portion of the second surface of the base layer,
wherein the continuous sidewall includes a second curvilinear sidewall extending entirely through the second lower protection layer, and a first curvilinear sidewall extending entirely through the first lower protection layer,
wherein an upper limit of the first curvilinear sidewall is at a vertical level the same as or lower than a vertical level of the second surface of the base layer, the upper limit being measured from (i) an interface between the first lower protection layer and the second lower protection layer toward (ii) an interface between the first lower protection layer and base layer, and
wherein the linear portion of the second surface of the base layer extends from the first curvilinear sidewall to an outer wall of the interposer.