| CPC H01L 23/49816 (2013.01) [H01L 23/5385 (2013.01); H01L 24/16 (2013.01); H01L 25/18 (2013.01); H01L 2224/16225 (2013.01)] | 20 Claims |
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1. A semiconductor package comprising:
a first wiring pad formed on a package substrate;
a first wiring connection part formed on the first wiring pad and including a wiring solder layer;
a second wiring pad formed apart from the first wiring pad on the package substrate;
a second wiring connection part formed on the second wiring pad and including a conductor;
an interposer substrate mounted on the first wiring connection part and the second wiring connection part, wherein a first substrate connection part and a second substrate connection part respectively electrically connected to the first wiring connection part and the second wiring connection part are arranged on a rear surface of the interposer substrate; and
a plurality of semiconductor chips mounted apart from each other in a two-dimensional (2D) manner on the interposer substrate, wherein each of the semiconductor chips is electrically connected to the interposer substrate via a chip connection pillar,
wherein a lower surface of the first wiring connection part is lower than an upper surface of the package substrate, and
wherein the first substrate connection part includes a first substrate solder layer contacting the upper surface of the package substrate and an upper surface of the first wiring connection part.
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