US 12,272,626 B2
Conductive members atop semiconductor packages
Makoto Shibuya, Tokyo (JP); Masamitsu Matsuura, Beppu (JP); Kengo Aoya, Beppu (JP); and Anindya Poddar, Sunnyvale, CA (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Feb. 28, 2022, as Appl. No. 17/683,074.
Prior Publication US 2023/0275007 A1, Aug. 31, 2023
Int. Cl. H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01)
CPC H01L 23/49555 (2013.01) [H01L 21/4842 (2013.01); H01L 21/565 (2013.01); H01L 23/3107 (2013.01); H01L 24/48 (2013.01); H01L 24/85 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48245 (2013.01); H01L 2224/73265 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a semiconductor die including a device side having a circuit;
a mold compound covering the semiconductor die and the circuit;
a first lead coupled to the circuit, the first lead having a gullwing shape and emerging from the mold compound in a first horizontal plane, the first lead having a distal end coincident with a second horizontal plane lower than a bottom surface of the mold compound; and
a second lead coupled to the circuit, the second lead emerging from the mold compound in the first horizontal plane, the second lead having at least one curved segment and a distal end positioned in a trench formed in a topmost surface of the mold compound.