US 12,272,623 B2
Semiconductor packages and methods for forming the same
Shin-Yi Yang, New Taipei (TW); Ming-Han Lee, Taipei (TW); and Shau-Lin Shue, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 4, 2023, as Appl. No. 18/230,284.
Application 18/230,284 is a division of application No. 17/367,530, filed on Jul. 5, 2021, granted, now 11,854,944.
Claims priority of provisional application 63/166,466, filed on Mar. 26, 2021.
Prior Publication US 2023/0378030 A1, Nov. 23, 2023
Int. Cl. H01L 21/00 (2006.01); H01L 23/48 (2006.01); H01L 23/482 (2006.01); H01L 23/528 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01)
CPC H01L 23/4822 (2013.01) [H01L 23/481 (2013.01); H01L 23/5286 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first integrated circuit die comprising:
a first device layer having a first side and a second side opposite the first side;
a first interconnect structure disposed on the first side of the first device layer; and
a second interconnect structure disposed on the second side of the first device layer;
a power line extending through the first device layer and in contact with the first interconnect structure and the second interconnect structure; and
a second integrated circuit die disposed over the first integrated circuit die, the second integrated circuit die comprising:
a third interconnect structure in contact with the second interconnect structure of the first integrated circuit die.