US 12,272,621 B2
Buried conductive structure in semiconductor substrate
Kan-Ju Lin, Kaohsiung (TW); Lin-Yu Huang, Hsinchu (TW); Min-Hsuan Lu, Hsinchu (TW); Wei-Yip Loh, Hsinchu (TW); Hong-Mao Lee, Hsinchu (TW); and Harry Chien, Chandler, AZ (US)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 17, 2022, as Appl. No. 17/807,476.
Prior Publication US 2023/0411242 A1, Dec. 21, 2023
Int. Cl. H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 29/45 (2006.01)
CPC H01L 23/481 (2013.01) [H01L 21/76898 (2013.01); H01L 29/401 (2013.01); H01L 29/41733 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/45 (2013.01); H01L 29/456 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure, comprising:
an epitaxial region disposed on a substrate and adjacent to a nanostructured gate layer and a nanostructured channel layer;
a first silicide layer disposed within a top portion of the epitaxial region;
a first conductive structure disposed on a top surface of the first silicide layer;
a second silicide layer disposed within a bottom portion of the epitaxial region; and
a second conductive structure disposed on a bottom surface of the second silicide layer and traversing through the substrate, wherein the second conductive structure comprises:
a first metal layer in contact with the second silicide layer; and
a second metal layer in contact with the first metal layer.
 
11. A structure, comprising:
a metal fill layer traversing through a bottom portion of a substrate;
a metal capping layer disposed on a top surface of the metal fill layer, wherein a top surface of the metal capping layer is above a top surface of the substrate;
a source/drain (S/D) region disposed on the substrate and comprising a first silicide layer within a top portion of the S/D region and a second silicide layer within a bottom portion of the S/D region, wherein a bottom surface of the second silicide layer is in contact with the top surface of the metal capping layer;
a S/D contact structure in contact with a top surface of the first silicide layer; and
a gate structure disposed adjacent to the S/D contact structure.
 
17. A structure, comprising:
a region disposed on a substrate and adjacent to a nanostructured gate layer and a nanostructured channel layer;
a first silicide layer disposed on the region;
a first conductive structure disposed on the first silicide layer;
a second silicide layer disposed on a bottom portion of the region; and
a second conductive structure disposed on a bottom surface of the second silicide layer and traversing through the substrate.