US 12,272,615 B2
Thermal mismatch reduction in semiconductor device modules
Seungwon Im, Seoul (KR); and Oseob Jeon, Seoul (KR)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US)
Filed on Apr. 15, 2022, as Appl. No. 17/659,363.
Prior Publication US 2023/0335459 A1, Oct. 19, 2023
Int. Cl. H01L 23/373 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/3735 (2013.01) [H01L 23/49838 (2013.01); H01L 23/49866 (2013.01); H01L 24/32 (2013.01); H01L 25/0655 (2013.01); H01L 2224/32225 (2013.01); H01L 2924/35121 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device assembly comprising:
a first direct-bonded-metal (DBM) substrate including:
a first ceramic layer, and
a first metal layer disposed on a first surface of the first ceramic layer, the first metal layer including:
a first portion having a first thickness; and
a second portion having a second thickness, the second thickness being greater than the first thickness, the second portion including a metal alloy having a coefficient of thermal expansion (CTE) in a range of 7 to 11 part-per-million per degrees Celsius (ppm/° C.);
a first semiconductor die having a first surface coupled with the second portion of the first metal layer;
a second DBM substrate including a second ceramic layer, and a second metal layer disposed on a first surface of the second ceramic layer, the second metal layer including a first portion having the first thickness, and a second portion having the second thickness and including the metal alloy; and
a second semiconductor die having a first surface coupled with the second portion of the second metal layer, and a second surface coupled with the first portion of the first metal layer,
a second surface of the first semiconductor die being coupled with the first portion of the second metal layer.