| CPC H01L 21/823878 (2013.01) [H01L 21/76224 (2013.01); H01L 27/11807 (2013.01); H01L 2027/11816 (2013.01); H01L 2027/11829 (2013.01); H01L 2027/11861 (2013.01)] | 17 Claims |
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1. A method of fabricating a semiconductor device, comprising:
forming an active pattern on a substrate by patterning the substrate;
forming a sacrificial pattern on the active pattern;
forming a gate spacer on a side surface of the sacrificial pattern;
forming a source/drain pattern on the active pattern, the source/drain pattern formed to be adjacent to the gate spacer;
replacing the sacrificial pattern with a gate dielectric pattern and a gate electrode, the gate dielectric pattern covering an inner surface of the gate spacer;
forming a hard mask pattern with an opening that vertically overlaps the gate electrode;
forming a hole exposing the active pattern through the gate electrode by performing an etching process using the hard mask pattern as an etch mask, the gate dielectric pattern on the inner surface of the gate spacer being exposed by the hole;
forming a first recess through an upper portion of the active pattern by performing an anisotropic etching process on the active pattern exposed by the hole; and
forming a separation structure by filling the hole and the first recess with an insulating layer,
wherein the filling of the hole and the first recess with the insulating layer includes:
forming a first insulating layer in the hole and the first recess;
forming a second insulating layer on the first insulating layer; and
forming a third insulating layer on the second insulating layer,
wherein a lowermost surface of the second insulating layer is lower than a lowermost surface of the first insulating layer, and
wherein a lowermost surface of the third insulating layer is lower than the lowermost surface of the second insulating layer.
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