US 12,272,605 B2
Methods of forming contact features in field-effect transistors
Yi-Hsiung Lin, Hsinchu County (TW); Yi-Hsun Chiu, Hsinchu County (TW); and Shang-Wen Chang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jun. 16, 2023, as Appl. No. 18/336,168.
Application 17/391,271 is a division of application No. 16/393,543, filed on Apr. 24, 2019, granted, now 11,081,403, issued on Aug. 3, 2021.
Application 18/336,168 is a continuation of application No. 17/391,271, filed on Aug. 2, 2021, granted, now 11,682,590.
Claims priority of provisional application 62/691,800, filed on Jun. 29, 2018.
Prior Publication US 2023/0326808 A1, Oct. 12, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/8238 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/823871 (2013.01) [H01L 21/76224 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 23/5226 (2013.01); H01L 27/0924 (2013.01); H01L 29/0847 (2013.01); H01L 29/6681 (2013.01); H01L 29/7851 (2013.01); H01L 2029/7858 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin, wherein the first and the second semiconductor fins extend lengthwise along a first direction over a substrate, and the first and the second semiconductor fins are spaced away from each other in a second direction perpendicular to the first direction;
a metal gate structure over the first semiconductor fin and the second semiconductor fin, the metal gate structure extending lengthwise along the second direction;
a first epitaxial source/drain (S/D) feature disposed over the first semiconductor fin;
a second epitaxial S/D feature disposed over the second semiconductor fin;
an interlayer dielectric (ILD) layer disposed over the first and the second epitaxial S/D features; and
an S/D contact disposed directly above the first and second epitaxial S/D features, wherein the S/D contact directly contacts the first epitaxial S/D feature, and the S/D contact is isolated from the second epitaxial S/D feature by the ILD layer.