US 12,272,603 B2
Method of manufacturing a semiconductor device and a semiconductor device
Hung-Li Chiang, Taipei (TW); Chih-Liang Chen, Hsinchu (TW); Tzu-Chiang Chen, Hsinchu (TW); I-Sheng Chen, Taipei (TW); and Lei-Chun Chou, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 7, 2023, as Appl. No. 18/504,027.
Application 17/114,347 is a division of application No. 16/281,679, filed on Feb. 21, 2019, granted, now 10,861,750, issued on Dec. 8, 2020.
Application 18/504,027 is a continuation of application No. 17/706,362, filed on Mar. 28, 2022, granted, now 11,848,242.
Application 17/706,362 is a continuation of application No. 17/114,347, filed on Dec. 7, 2020, granted, now 11,289,384, issued on Mar. 29, 2022.
Claims priority of provisional application 62/693,180, filed on Jul. 2, 2018.
Prior Publication US 2024/0071834 A1, Feb. 29, 2024
Int. Cl. H01L 29/76 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/94 (2006.01); H01L 31/112 (2006.01)
CPC H01L 21/823821 (2013.01) [H01L 21/823828 (2013.01); H01L 21/823864 (2013.01); H01L 21/823871 (2013.01); H01L 27/0924 (2013.01); H01L 29/0673 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 2029/7858 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
first well region and a second well region spaced apart from each other extending in a first direction and arranged in a second direction perpendicular to the first direction disposed over a substrate;
a first stack of spaced-apart semiconductor layers disposed over the first well region and a second stack of spaced-apart semiconductor layers disposed over the second well region,
wherein the first stack and the second stack are arranged along a third direction perpendicular to the first direction and the second direction, and
wherein a ratio of a height H2 of the first stack to a distance S4 between the first stack and the second stack (H2/S4) ranges from 0.25 to 5.0;
a metal track disposed between the first well region and the second well region;
a gate electrode wrapping around each of the semiconductor layers; and
an insulating layer disposed between the metal track and the gate electrode along the third direction.