| CPC H01L 21/823814 (2013.01) [H01L 21/28518 (2013.01); H01L 27/0924 (2013.01)] | 20 Claims |

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1. A method of fabricating a semiconductor device, comprising:
forming an n-type source/drain feature over a first fin and a p-type source/drain feature over a second fin;
selectively depositing a p-type epitaxial capping layer over the n-type source/drain feature;
selectively depositing an n-type epitaxial capping layer over the p-type source/drain feature;
depositing a dielectric layer over the p-type epitaxial capping layer and the n-type epitaxial capping layer;
forming a first opening through the dielectric layer to expose the p-type epitaxial capping layer;
forming a second opening through the dielectric layer to expose the n-type epitaxial capping layer;
selectively depositing a first metal layer over the second opening to contact the n-type epitaxial capping layer;
depositing a second metal layer over the first opening and the second opening to contact the p-type epitaxial capping layer and the first metal layer;
depositing a capping layer over the second metal layer;
after the depositing of the capping layer, annealing the n-type source/drain feature and the p-type source/drain feature; and
after the annealing, deposit a contact metal layer of the capping layer.
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