	US 12,272,601 B2
	Epitaxial high-K etch stop layer for backside reveal integration
Robert D. Clark, Fremont, CA (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on Sep. 22, 2021, as Appl. No. 17/481,512.
Claims priority of provisional application 63/082,926, filed on Sep. 24, 2020.
Prior Publication US 2022/0093466 A1, Mar. 24, 2022
Int. Cl. H01L 21/78 (2006.01); H01L 21/306 (2006.01); H01L 21/311 (2006.01); H10D 86/01 (2025.01)

CPC H01L 21/7806 (2013.01) [H01L 21/30621 (2013.01); H01L 21/31116 (2013.01); H10D 86/0214 (2025.01)]

9 Claims

1. A backside reveal method, comprising:

providing a semiconductor material substrate;

depositing an epitaxial high-k etch stop layer on the semiconductor material substrate,

forming an integrated circuit device layer on the epitaxial high-k etch stop layer;

attaching a carrier substrate to a front side of the integrated circuit device layer;

removing a portion of a thickness of the semiconductor material substrate to leave a remaining portion of the thickness of the semiconductor material substrate;

removing, by a first selective etching, the remaining portion of the semiconductor material substrate; and

removing, by a second selective etching, the epitaxial high-k etch stop layer to expose a backside of the integrated circuit device layer, wherein the epitaxial high-k etch stop layer includes a mixed metal oxide with the chemical formula Ln¹_xLn²_yO_(x+y)3/2, wherein Ln¹and Ln²are selected from Scandium (Sc), Yttrium (Y), and the lanthanide series.