US 12,272,585 B2
Wafer chuck structure with holes in upper surface to improve temperature uniformity
Ting-Jung Chen, Kaohsiung (TW); Shih-Wei Lin, Taipei (TW); and Lee-Chuan Tseng, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 27, 2021, as Appl. No. 17/241,666.
Prior Publication US 2022/0344193 A1, Oct. 27, 2022
Int. Cl. H01L 21/683 (2006.01); C23C 14/50 (2006.01); C23C 14/54 (2006.01); C23C 14/58 (2006.01); C23C 16/458 (2006.01); C23C 16/46 (2006.01); H01J 37/32 (2006.01); H01L 21/67 (2006.01); H01L 21/768 (2006.01)
CPC H01L 21/6833 (2013.01) [C23C 14/50 (2013.01); C23C 14/541 (2013.01); C23C 14/5873 (2013.01); C23C 16/4586 (2013.01); C23C 16/466 (2013.01); H01J 37/32724 (2013.01); H01L 21/67109 (2013.01); H01J 2237/002 (2013.01); H01J 2237/2007 (2013.01); H01L 21/67069 (2013.01); H01L 21/76802 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a layer over a wafer;
forming a masking structure over the layer;
transporting the wafer onto a wafer chuck structure arranged within a processing chamber, wherein the wafer chuck structure comprises a lower portion having a trench coupled to a cooling gas pipe, wherein the wafer chuck structure comprises an upper portion arranged over the lower portion and comprising a hole extending completely through the upper portion and directly overlying the trench, wherein the hole extends from a top surface of the wafer chuck structure to a top surface of the trench, wherein the hole has a first width at the top surface of the wafer chuck structure and a second width directly below the first width, the first width being larger than the second width;
turning the wafer chuck structure ON to electrostatically hold onto the wafer during processing;
turning a cooling gas source ON such that a cooling gas flows through the first width and the second width of the cooling gas pipe, the trench and the hole to evenly distribute the cooling gas towards a backside of the wafer; and
performing a removal process to remove portions of the layer according to the masking structure while the cooling gas source is ON.