US 12,272,561 B2
Method for manufacturing semiconductor device
Li-Han Lin, Taoyuan (TW); Jr-Chiuan Wang, New Taipei (TW); and Szu-Yu Hou, New Taipei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Jun. 1, 2022, as Appl. No. 17/829,699.
Prior Publication US 2023/0395388 A1, Dec. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/311 (2006.01); H01L 21/768 (2006.01); H10B 12/00 (2023.01)
CPC H01L 21/31111 (2013.01) [H01L 21/31144 (2013.01); H01L 21/76825 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H10B 12/482 (2023.02); H10B 12/485 (2023.02); H01L 21/76816 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor device, comprising:
forming a first insulating layer having a bit line contact over a substrate;
forming a second insulating layer having a bit line opening over the first insulating layer;
forming a bit line structure in the bit line opening, the bit line structure being electrically connecting to the bit line contact, and a contact void being formed surrounding the bit line structure and partially exposing a surface of the bit line contact;
conformally forming a nitride spacer layer over the bit line structure, the second insulating layer, and the contact void;
conformally forming a plasma oxide layer over the nitride spacer layer;
forming a nitride capping layer over the plasma oxide layer, the nitride capping layer filling the contact void; introducing nitrogen ions into a surface of the nitride capping layer surrounding the bit line structure; and
performing an etching back process to remove a portion of the nitride capping layer, thereby forming a refilled contact void between the second insulating layer and the bit line structure.