US 12,272,550 B2
Method of fabricating thin, crystalline silicon film and thin film transistors
Ramesh Kumar Harjivan Kakkad, New Taipei (TW)
Filed by Ramesh Kumar Harjivan Kakkad, New Taipei (TW)
Filed on Sep. 13, 2023, as Appl. No. 18/466,644.
Application 18/466,644 is a division of application No. 16/938,851, filed on Jul. 24, 2020, granted, now 11,791,159.
Application 16/938,851 is a continuation in part of application No. 16/745,912, filed on Jan. 17, 2020, granted, now 11,562,903, issued on Jan. 24, 2023.
Claims priority of provisional application 62/963,439, filed on Jan. 20, 2020.
Claims priority of provisional application 62/944,446, filed on Dec. 6, 2019.
Claims priority of provisional application 62/793,437, filed on Jan. 17, 2019.
Prior Publication US 2023/0420253 A1, Dec. 28, 2023
Int. Cl. H01L 21/02 (2006.01); H01L 29/167 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/02667 (2013.01) [H01L 21/0245 (2013.01); H01L 21/02532 (2013.01); H01L 21/02573 (2013.01); H01L 21/02592 (2013.01); H01L 21/02672 (2013.01); H01L 29/167 (2013.01); H01L 29/66757 (2013.01); H01L 29/78675 (2013.01); H01L 21/02496 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A method of producing a polycrystalline silicon thin film transistor, comprising:
forming nickel patterns on a substrate;
forming a phosphorus doped silicon layer over the substrate and the nickel patterns, the phosphorus doped silicon layer being amorphous at formation;
forming a first silicon layer on the phosphorus doped silicon layer, the first silicon layer being amorphous at formation, the first silicon layer including intrinsic silicon;
annealing the phosphorus doped silicon layer, the first silicon layer, and the nickel patterns to cause crystallization of the phosphorus doped silicon layer, and the first silicon layer, wherein the crystallization propagates by a combination of lateral crystal growth between the nickel patterns and vertical crystal growth to crystallize the phosphorus doped silicon layer, and the first silicon layer.