US 12,272,498 B2
Multilayer ceramic capacitor
Hiroyasu Yoshida, Nagaokakyo (JP)
Assigned to MURATA MANUFACTURING CO., LTD., Kyoto (JP)
Filed by Murata Manufacturing Co., Ltd., Nagaokakyo (JP)
Filed on Oct. 18, 2021, as Appl. No. 17/503,416.
Claims priority of application No. 2020-183729 (JP), filed on Nov. 2, 2020.
Prior Publication US 2022/0139631 A1, May 5, 2022
Int. Cl. H01G 4/30 (2006.01); H01G 4/012 (2006.01); H01G 4/12 (2006.01); H01G 4/232 (2006.01)
CPC H01G 4/30 (2013.01) [H01G 4/012 (2013.01); H01G 4/12 (2013.01); H01G 4/232 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A multilayer ceramic capacitor comprising:
a multilayer body including:
a laminate chip and side gap portions, the laminate chip including an inner layer portion in which dielectric layers and internal electrode layers are alternately laminated, and outer layer portions respectively on both sides of the inner layer portion in a lamination direction, and the side gap portions respectively on both sides of the laminate chip in a width direction perpendicular or substantially perpendicular to the lamination direction; and
external electrodes on both sides of the multilayer body in a length direction intersecting the lamination direction and the width direction; wherein
when a thickness of one of the outer layer portions is defined as T1, and a thickness of one of the side gap portions is defined as W1, W1 and T1 are about 20 μm or less, and about 0.1<| (W1-T1)|/T1<about 0.3 is satisfied;
the side gap portions sandwich and cover the outer layer portions in the width direction, and cover the internal electrode layers along end portions of the internal electrode layers in the width direction; and
an interface is provided between the side gap portions and the outer layer portions.