US 12,272,484 B2
Coreless electronic substrates having embedded inductors
Srinivas Pietambaram, Chandler, AZ (US); Pooya Tadayon, Portland, OR (US); Kristof Darmawikarta, Chandler, AZ (US); Tarek Ibrahim, Mesa, AZ (US); and Prithwish Chatterjee, Tempe, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 4, 2021, as Appl. No. 17/192,187.
Prior Publication US 2022/0285079 A1, Sep. 8, 2022
Int. Cl. H01F 27/28 (2006.01); H01F 1/04 (2006.01); H01F 27/40 (2006.01); H05K 1/16 (2006.01)
CPC H01F 27/2804 (2013.01) [H01F 1/04 (2013.01); H01F 27/40 (2013.01); H05K 1/165 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of metallization levels with one or more layers of dielectric material between the levels, wherein each of the metallization levels comprises a plurality of coplanar metallization traces;
a first high-permeability magnetic ferrite element within the dielectric material, the first high-permeability magnetic ferrite element in direct contact with a first surface of a coiled one of the metallization traces in a first of the metallization levels; and
a second high-permeability magnetic ferrite element within the dielectric material, the second high-permeability magnetic ferrite element in direct contact with a second surface of the coiled one of the metallization traces, opposite the first surface, and in direct contact with a portion of the first high-permeability magnetic ferrite element extending between turns of the coiled one of the metallization traces.