US 12,272,428 B2
Command address control circuit and semiconductor apparatus and semiconductor system including the command address control circuit and semiconductor apparatus
Se Ra Jeong, Icheon-si (KR); Kyung Hoon Kim, Icheon-si (KR); Ji Hwan Park, Icheon-si (KR); Ha Jun Jeong, Icheon-si (KR); and Jae Hoon Cha, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Sep. 1, 2022, as Appl. No. 17/901,159.
Claims priority of provisional application 63/240,292, filed on Sep. 2, 2021.
Claims priority of application No. 10-2022-0091308 (KR), filed on Jul. 22, 2022.
Prior Publication US 2023/0062952 A1, Mar. 2, 2023
Int. Cl. G11C 8/18 (2006.01); G11C 8/06 (2006.01); G11C 29/52 (2006.01)
CPC G11C 8/18 (2013.01) [G11C 8/06 (2013.01); G11C 29/52 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor apparatus comprising a command address control circuit configured to:
receive a row command address signal and a column command address signal, and
invert all bits of the row command address signal and the column command address signal when at least one bit within the row command address signal is at a first logic level, and non-invert all bits of the row command address signal and the column command address signal when the at least one bit within the row command address signal is at a second logic level.